Top of page

Font Size

Content Area

Organization & Research Areas

Metro-Access Network Device Project

The metro-access network device project promotes the research and development of device technology to achieve the next generation of metro-access networks and the expansion of data centers to accommodate the rapidly increasing traffic due to the spread of video services, smartphones, and cloud services. Our practical development of access control LSI, compact optical sub-assembly modules, and FPGA NIC for SDN software switches aims to contribute to the creation of the next generation of communications services and networks with advanced  and low power consumption.

Figure of Metro-Access Network Device Project

Next-generation access control LSI

We are developing a access control LSI, which is a small semiconductor chip, to handle access communications networks. We have already developed an access control LSI for GE-PON ONUs, which is used for NTT‘s FTTH service called “B-FLET’s,” and an LSI chipset for 10G-EPON OLTs and ONUs, which has ten times wider bandwidth than conventional GE-PON. Our LSI  in development is the key to realizing mobile-access convergence networks for low-cost, low-power, and high-performance access service.

Figure of Mobile-access convergence network


*FTTH: Fiber to the home
*LSI: Large scale integrated circuits
*ONU: Optical network unit
*10G-EPON: 10 Giga bit ethernet passive optical network

Optical Sub-Assembly Module 400GbE TOSA/ROSA

Traffic both within and between datacenters is rapidly increasing as the demand for cloud computing and mobile services grows. Small size and low power consumption are demanded for the optical transceivers in the data center network., We are using sub-micrometer semiconductor fabrication process and opto-electronics integration technologies to develop optical sub-assembly modules (TOSA/ROSA), which are the key components for realizing such transceivers. We have already developed an APD-ROSA by integrating our original APD array and a PLC demultiplexer into one package. Our APD-ROSA is the only device to meet the requirements for > 20-km transmission in practical use. Our current challenge is to develop a faster TOSA/ROSA for 400-GbE application.

Figure of Optical Sub-Assembly Module


*GbE: Giga bit ethernet
*TOSA: Transmitter optical sub-assembly
*ROSA: Receiver optivcal sub-assembly
*APD: Avalanche photodiode
*PLC: Planer lightwave circuit

FPGA NIC for SDN software switch

Nowadays, a network needs to be constructed quickly and flexibly. SDN and NFV are technologies for easily customizing a network. We developed an FPGA-NIC accelerator to improve the data-plane transfer rate of both an SDN software switch and an NFV application. The accelerator achieved data transfer at a 40-Gbps wire-speed in cooperation with an SDN software switch named "Lagopus". We are currently working on improving the accelerator's [Lagopus's] performance and functionality for practical use.

Figure of FPGA NIC for SDN software switch


*SDN : Software Defined Networking
*NFV : Network Functions Virtualization
*FPGA : Field Programmable Gate Array
*DPDK : Data Plane Development Kit
*PMD : Poll Mode Driver
*API : Application Programming Interface

Sub Content Area
Footer Area
Copyright © 2016 Nippon Telegraph and Telephone Corporation