October 16, 2018
Nippon Telegraph and Telephone Corporation (NTT; Head office: Chiyoda-ku, Tokyo; President & CEO: Jun Sawada) has succeeded in combining a high-speed DAC (digital-to-analog converter) (*1) architecture with waveform quality enhancement technology to generate PAM4 (*2) coded signals (which are starting to be adopted in Ethernet and other networks) at a rate of 256 Gbps.
In Ethernet and other short-range optical communication technologies that are used in datacenters, intensity modulation (*3) schemes with a simple optical component configuration are used in order to satisfy energy-saving and economic requirements. A type of intensity modulation called PAM4 coding has recently grown in popularity as a way of meeting the demand for increased capacity. In PAM4 coding, the information to be transmitted must be transformed into multilevel analog voltages. However, it was found to be difficult to generate high-speed and high-quality multilevel voltage waveforms sufficient for 256 Gbps transmission.
At NTT, we have succeeded in generating 256 Gbps multilevel voltage signals (at a symbol rate of 128 Gbaud) by using InP (*4) -HBT (*5) to fabricate a PAM4 signal generator circuit incorporating our proprietary high-speed DAC architecture technology and waveform enhancement technology. We expect this ultra-high-speed IC technology will be used for short-range high-capacity communication in datacenters and other facilities, leading to the realization of transmission speeds of the order of 1 Tbps (*6), which is ten times faster than the 100 Gbps Ethernet technology that is currently in widespread use (based on 25 Gbps optical signals multiplexed across four lanes). Details of this technology are due to be presented at the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS 2018), to be held in San Diego, California, from 14th October.
Short-range communication technologies such as Ethernet are required for low-cost, compact low-power transceiver equipment in data centers and other such facilities. Conventional short-range communication uses a NRZ (non-return-to-zero) code that transmits data as a pulse signal with two levels. For higher transmission capacity, the use of PAM4 coding is being introduced. This is a modulation scheme where data is transmitted as a pulse signal with four levels (Fig. 1). In PAM4 coding, the transmitted data must be transformed into multilevel analog voltages, but it has been difficult to generate multilevel voltage waveforms of sufficient speed and quality for 256 Gbps transmissions.
By using InP-HBT process technology (Fig. 4) together with our proprietary high-speed DAC architecture and waveform quality enhancement technology (Figs. 2, 3), we have succeeded in fabricating a PAM4 signal generator circuit capable of generating 256 Gbps multilevel voltage signals at a symbol rate of 128 Gbaud (Fig. 5). In 100 Gbps Ethernet technology, which is currently in widespread use, optical signals are multiplexed across four lanes, each with a capacity of 25 Gbps. By doubling the number of signal levels and increasing the signaling speed by a factor of five, we have succeeded in developing the world’s first ultra-high-speed IC capable of generating PAM4 signals with a data rate of 256 Gbps per lane (ten times that of current practical technology) (Fig. 6).
This ultra-high-speed IC can generate high-quality multilevel voltage signals with a high symbol rate (128 Gbaud), which has so far been difficult to achieve. It is therefore expected to find applications in the R&D of innovative devices with symbol rates of 100 Gbaud to 128 Gbaud for next-generation large-capacity communication systems, and in measuring instrument (signal generators) for system verification. We also expect this technology to lead to developments in fields such as large-capacity optical communication that require high-speed multilevel signals and large-capacity optical communications, including four-lane multiplexing to achieve 1 Tbps transmission. At NTT, by cooperating with our partners, we aim to create new services and industries using ultra-high-speed ICs, and to promote the continued evolution of ultra-high-speed IC technology (*7).
We have realized a PAM4 signal generator circuit (Fig. 2) by applying our proprietary high-speed DAC architecture technology and waveform enhancement technology. In general, DAC require that multi-bit digital signals are input at the same speed as the symbol rate of the generated analog signal, and this digital input interface has limited the operating speed of the DAC as a whole. Also, the operation of DACs at high speed has given rise to problems such as waveform distortion due to skew (temporal shifts) between bits inside the DAC, and noise due to leakage of the clock signal into the data signals.
In this technology, by applying our proprietary high-speed DAC architecture technology, which uses a high-speed selector circuit (SEL) to provide half-rate inputs, together with our waveform enhancement technology with a distortion compensation delay circuit and noise rejection buffer, we can dramatically improve the operating speed and waveform quality. Following the fabrication of a PAM4 signal generation circuit using our in-house InP-HBT technology, we have succeeded in generating multilevel voltage signals at a rate of 256 Gbps.
Science and Core Technology Group
Nippon Telegraph and Telephone Corporation
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